|
|
Software-defined radios underpin many deployed wireless systems, but host-centric streaming becomes unreliable at high bandwidths, with many antennas, and when time-granular control is required. The root difficulty is a timing-domain mismatch: the FPGA and RF front-end run on a deterministic, clock-driven timeline locked to the RF sampling clock, while the host runs asynchronously under OS scheduling, interrupts, and queueing delay. Traditional stacks resolve this by forcing the host to keep pace with the radio, so an ordinary context switch can leave the buffer running dry. At wideband rates this produces underflows, overflows, and late commands. Modern applications need all four of continuous wideband streaming, RF synchronization across channels, slot-level control, and easy programmability — and existing platforms support only one or two.
We present RadioStream, a radio-centric, slot-synchronous SDR architecture in which the host and radio coordinate using slots (a pre-defined unit of time) rather than individual sample transfers. The FPGA owns slot timing and all time-critical radio actions, and exports slot boundaries as 64-byte slot-tick Ethernet packets. The host programs future slots against that timeline, and the FPGA applies every radio-visible update only at slot boundaries, with control and data both tagged by slot number. Slot-aligned buffering and a two-slot look-ahead absorb transport delay and host jitter, so the host can stay fully asynchronous while radio behavior remains deterministic. A lightweight three-packet fronthaul (slot ticks, jumbo-frame data, fixed-size control) runs over 100 GbE, and a DPDK-based host path hands samples to applications such as GNU Radio, Python, and MATLAB through shared memory, with no kernel in the way.
We implement RadioStream on the Xilinx XCZU48DR RFSoC, prototyping on both the commercially available RFSoC 4x2 board and a custom 8T8R platform: an RFSoC system-on-module paired with an RF board carrying dual QSFP28 cages, SMA connectors for all eight TX and eight RX chains, PL-side DDR4 for slot-indexed IQ buffering, and a zero-delay-multiplier clock circuit that drives all ADC and DAC tiles to eliminate inter-tile skew. The design stays lightweight on the FPGA, leaving over 84% of LUTs and 99% of DSPs free for additional processing blocks.
On a 100 Gbps interface, RadioStream sustains 90 Gbps concurrently on uplink and downlink with no packet drops across a 5-hour experiment, and streams 2 GHz of aggregated RF bandwidth. Slot-tick jitter measured at the host stays near 113 ns at the median and under 600 ns at the 99th percentile, confirming that the FPGA remains the timing master while the host simply follows that timeline. Per-slot control reaches the RF output in under 500 ns, measured on an NCO frequency update. Against a commercial USRP X410 baseline given more CPU cores, RadioStream is lossless where the X410 drops 99% of samples at 1966.08 Msps, using only three cores.
We demonstrate these capabilities on three workloads sharing the same timing, transport, and control substrate. A point-to-point 28 GHz link carries a continuous 5G NR OFDM waveform with stable 4–6% EVM, and a 491.52 MHz WiFi waveform yields clean 64-QAM and 256-QAM constellations. A mmWave beam-sweeping experiment sweeps the receiver across azimuth and selects the correct beam to within 2.5°, with only 0.5 dB SNR loss. Finally, a sub-6 GHz multi-antenna capture resolves two sources in joint angle and range: moving from 2 antennas to 4 sharpens the angular profile, and raising bandwidth to 491.52 MHz improves distance resolution from 2.4 m to 0.6 m.
|
|